AP9950/9951 43.5-GBPS Bit Error Rate Tester

BANNO Noriyuki¹ AKAHORI Hiroshi¹ HARA Kiyomi¹ KOYANAGI Nobuo²

AP9950 pulse pattern generator (PPG) and AP9951 error detector (ED), each having independent compact hardware of 425 (W) × 221 (H) × 500 (D) mm in size, were developed to compose a bit error rate tester (BERT) for the 40-Gbps bit rate band. These PPG and ED offer measurement of bit error rates in the 40-Gbps band (36 through 43.5 Gbps) with four parallel channels of 10-Gbps band inputs and outputs, and feature a wealth of measurement patterns, an auto-search feature, and burst signal measurement. They are thus ideal for development, manufacturing, verification, and testing of transmission systems as well as for devices and modules used in those systems.

1. Ando Electric Co., Ltd.
2. Communications Business Center Figure 1 Models AP9950 (upper) and AP9951 (lower)

INTRODUCTION

As the popularity of broadband communications has risen sharply and is moving forward in the access lines recently, an anticipated explosion in transmission capacity has been driving the research and development of 40-Gbps optical communication systems. Instruments used to measure the bit error rate of a transmission system, which is a basic transmission characteristic, are required to be more compact and give higher performance. To meet this demand, we developed a bit error tester having a body nearly four times smaller in comparison to conventional rack-mounted testers. This new tester is designed to be comprised of two separate housings, one as Model AP9950 pulse pattern generator (PPG) and one as Model AP9951 error detector (ED), achieving drastically improved operability and portability. In addition, Yokogawa-developed, ultra-highspeed heterojunction bipolar transistor (HBT)-based IC modules employed in the multiplexer (MUX) unit of the PPG and in the demultiplexer (DEMUX) unit of the ED, have achieved refinements in waveform quality. Figure 1 shows this unit.

FEATURES

Figure 1 Models AP9950 (upper) and AP9951 (lower)

The features of the AP9950 and AP9951 include the following:

1. Compact, lightweight, and highly portable
2. Covers the 40-Gbps bit rate band (36 through 43.5 Gbps)
3. Four parallel channels of 10-Gbps band inputs and outputs (in 10-Gbps mode):
   • Four 10-Gbps band channel signals for MUX/DEMUX (inputs to the multiplexer or outputs from the demultiplexer)
   • Four independent signals of 10-Gbps band
4. A wealth of measurement patterns:
   • PRBS7, PRBS9, PRBS10, PRBS11, PRBS15, PRBS23, and PRBS31 (pseudo random binary sequence)
   •  Programmable patterns of 1 to 8 Mbits in length
   •  Synchronous digital hierarchy (SDH) frame patterns (Bulk or CID)
5. Auto-search
6. Burst signal measurement

APPLICATIONS

Figure 2 Examples of Applications

Figure 2 shows examples of applications of the AP9950 and AP9951. In these applications, a pseudo random binary sequence or sequences generated by the AP9950 pulse pattern generator are input to the device under testing, and the device's output or outputs is detected and analyzed to monitor the bit error rate. Not limited to these examples, combined use of 40-Gbps and 10-Gbps interfaces will enable testing of various devices.

ARCHITECTURE OF AP9950 PULSE PATTERN GENERATOR

Figure 3 Internal Architecture of AP9950 Pulse Pattern Generator

Figure 3 illustrates the internal architecture of the AP9950.

Internal Architecture

The AP9950 contains a CPU and a power supply unit comprising the platform, which is connected via an internal bus to signal generator, pattern generator, 10G-MUX, and 40G-MUX units, as shown in Figure 3. The following details these units.

Signal Generator Unit

The signal generator unit consists of a reference frequency generation circuit, a main phase-locked loop (PLL) circuit which generates a 10-GHz band signal, a clock doubler, an external sync signal input circuit, and a switching circuit, as illustrated in Figure 4.

The reference frequency generation circuit is comprised of a reference frequency crystal oscillator, a minute frequency adjuster circuit consisting of a voltage-controlled oscillator (VCO) and a commercial-off-the-shelf fractional-N frequency divider IC, a quadrature modulator, and a band pass filter (BPF). The minute frequency adjuster generates a 1-GHz band signal, which is then frequency-divided to raise the signal quality. Then, the resulting signal is frequency-synthesized by the reference frequency crystal oscillator and quadrature modulator to suppress the unnecessary frequency components such as the reference frequency generated by the crystal oscillator. These unnecessary frequency components are further eliminated through the BPF to deliver a reference signal.

Figure 4 Signal Generator Unit Configuration

The main PLL circuit is comprised of a yig-tuned oscillator (YTO) which serves as a VCO, a fixed-frequency divider, a highspeed fractional-N frequency divider circuit which consists of a programmable divider and memory, a phase comparator, and a loop filter. The frequency divider circuit functions in such a way that frequency-divided data written to the field programmable gate array (FPGA) configuration memory is sequentially read, thus achieving highspeed fractional-N frequency division. This PLL circuit can deliver a 10-GHz band signal with its frequency variable in approximately 10-kHz steps. The output is multiplied into a 20-GHz band signal through the clock doubler.

The external sync signal input circuit produces a reference signal based on the division denominator K that is adjustable as appropriate for each of the 10-GHz, 2.5-GHz, 600-MHz, and 150- MHz band input signals. This reference signal is input to the main loop, thereby producing a 20-GHz band output signal synchronized with the external sync signal.

The following shows the general specifications of the signal generator unit:

• Frequency range: 19.5 to 22.5 GHz
• Frequency adjustment: In 0.5 kHz steps
• SSB phase noise (typical at 19.9 GHz):
  –85 dBc/Hz (at 1 kHz offset)
  –93 dBc/Hz (at 10 kHz offset)
  –103 dBc/Hz (at 100 kHz offset)
  –125 dBc/Hz (at 1 MHz offset)

Pattern Generator Unit

Figure 5 Pattern Generator Unit Configuration

The pattern generator unit receives a 622-MHz (562.5 through 679.7 MHz) band clock signal, generates an PRBS pattern, a programmed pattern, and an SDH frame pattern, and outputs it to the 10G-MUX unit. Figure 5 illustrates the pattern generator unit configuration.

The pattern generator unit consists of a frequency divider circuit, a pattern generation circuit, and a 512:64 MUX circuit.

The frequency divider circuit divides the 622-MHz band clock into 78-MHz band clocks and distributes them to other circuits such as the pattern generation circuit. In addition, the divider circuit advances the clocks' phases to cancel the propagation delays using a PLL so as to enable the 10G-MUX unit to perform data sampling.

In the 40-GHz mode, the pattern generation circuit generates 512 channels of 78-Mbps band (70 through 85 MHz) signals to generate various bit stream patterns such as a PRBS. In the 10- GHz mode, it generates 128 channels of 78-Mbps band signals for each of 4 lines to enable generation of 4-channel bit streams of different patterns equivalent to 10-Gbps data. Having an FPGA configuration, this pattern generation circuit is flexibly modifiable with function upgrades. The 512:64 MUX circuit, which is comprised of sixty-four 8:1 MUXs, multiplexes the 512 channels of 78-Mbps band signals into 64 channels of 622-Mbps band signals and outputs them to the 10G-MUX unit.

10G-MUX Unit

Figure 6 10G-MUX Unit Configuration

The 10G-MUX unit performs the 64:4 multiplexing, data output for 2 lines — one to the 40G-MUX and one to the front panel terminals — and trigger output. Figure 6 shows the functional block diagram.

The 64:4 MUX consists of four 16:1 multiplexers, a synchronization circuit which synchronizes these four multiplexers, and a lock (synchronized state) detect circuit, multiplexes 64 pairs of 622-Mbps band data streams into four 10- Gbps band data streams, and outputs them in synchronized timings.

The multiplexed 10-Gbps band data streams are re-timed by a D flip-flop (DFF), then output to the 40G-MUX unit. Concurrently, four 10-Gbps band data streams and a 10-GHz band clock signal are output to terminals on the front panel through an output buffer which allows the output to be switched on and off.

To shorten the propagation delays occurring between the signal generation before the 10G-MUX and its multiplexing circuit, a PLL configuration feedback loop which takes a delay into account is used in the clock signal circuit. This resulted in phase lead of 10-Gbps band output data streams and the shortened delay time of the clock signal for the 40G-MUX unit.

The trigger circuit offers multi-triggers and can output a 1/4, 1/64, or 1/256 clock trigger, or a pattern synchronous trigger at working frequencies from 9 through 10.875 Gbps.

40G-MUX Unit

Figure 7 40G-MUX Unit Configuration

Figure 7 illustrates the 40G-MUX unit configuration. This unit performs time division multiplexing for the four data streams from the 10G-MUX unit to ultimately produce a 40-Gbps band data stream. Yokogawa-developed logic ICs such as the 4:1 MUX module are used for the multiplexing. The 40-Gbps band data stream is wave-shaped by a DFF and output via a driver amplifier. Use of a DFF enables delivery of a uniform data signal with low waveform distortion and jitters. Data at bit rates from 36 through 43.5 Gbps can be output with no need of adjustment.

As for clock signal generation, a timing generator receives an external 20-GHz band signal (from a synthesizer), produces 20- GHz and 40-GHz band clock signals, and supplies them to the 4:1 MUX module and DFF, as well as supplies 10-GHz clock signals to the outside via a delay line, amplifier, and variable attenuator.

ARCHITECTURE OF AP9951 ERROR DETECTOR

Figure 8 Internal Architecture of AP9951 Error Detector

Figure 8 illustrates the internal architecture of the AP9951.

Internal Architecture

The AP9951 contains a CPU and a power supply unit comprising the platform, which is connected via an internal bus to error measurement, 10G-DEMUX, and 40-Gbps DEMUX units. The following details these units.

Error Measurement Unit

The error measurement unit receives a 622-MHz band (562.5 through 679.7 MHz) clock signal and 622-Mbps band (562.5 through 679.7 Mbps) data from the 10G-DEMUX unit, and monitors the out-of-synchronization time with repetitive patterns and bit error rates. As illustrated in Figure 9, the error measurement unit consists of a clock divider circuit, a 64:512 DEMUX circuit, and a measurement circuit.

Figure 9 Error Measurement Unit Configuration

The divider circuit divides a 622-MHz band clock signal into eight 78-MHz band (70 through 85 MHz) clock signals and distributes them to the measurement circuit and so on. It also advances the phases of these divided clock signals with a PLL to cancel the propagation delays occurring in the clock division and internal circuits.

The 64:512 DEMUX circuit is comprised of 64 1:8 DEMUXs and separates the 64 channels of 622-Mbps band data into 512 channels of 78-Mbps band data.

To synchronize the input data to bit patterns such as a PRBS and to measure bit error rates, in the 40-Gbps mode, the measurement circuit generates 512 channels of 78-Mbps band reference data patterns, and synchronizes the input data to them to measure the bit error rates. In the 10-Gbps mode, the measurement circuit generates 128 channels of 78-Mbps band reference data patterns for four input lines, and synchronizes the individual input data to them to measure the bit error rates. For the four 10-Gbps equivalent inputs, synchronization with different patterns can be monitored. This circuit has an FPGA configuration for flexibility with future upgrades. The software displays the measured results on the screen.

10G-DEMUX Unit

Figure 10 10G-DEMUX Unit Configuration

The 10G-DEMUX unit selects four pairs of clock and data inputs from two lines, has a variable phase shifter for the clock input, and demultiplexes 4 bit streams into 64. Its configuration is illustrated in Figure 10.

Either the inputs from terminals on the front panel or outputs from the 40G-DEMUX unit can be chosen as the 10-GHz band clock and 10-Gbps band data inputs. The four 10-Gbps band data inputs from the front panel are wave-shaped by DFFs based on the input clock signal through a variable phase shifter and in accordance with a variable threshold. The 4:64 DEMUX demultiplexes the selected clock and data streams at operating frequencies of 9 through 10.875 Gbps. Similar to the 10G-MUX unit in the AP9950 pulse pattern generator, this 10G-DEMUX unit is comprised of four 1:16 demultiplexers, and a synchronization circuit which synchronizes these four demultiplexers, and a lock (synchronized state) detect circuit. It demultiplexes four 10-Gbps band data streams into 64 pairs of 622-Mbps band data streams, and outputs them in synchronized timings.

40G-DEMUX Unit

Figure 11 40G-DEMUX Unit Configuration

As illustrated in Figure 11, the 40G-DEMUX unit demultiplexes a 40-Gbps band data stream into four 10-Gbps band data streams with a Yokogawa-developed ultra-highspeed HBT-based 1:4 demultiplexer module, and outputs them to the 10G-DEMUX unit.

The 40-Gbps band data stream input from the outside is synchronized to a 40-GHz band clock signal by a DFF. This wave shaping of the input data stream achieves a favorable sensitivity and phase margin. A high-precision delay line is adopted for adjustment of the input signal timing, and a preamplifier to be connected externally is provided to enable handling of input signals of minute levels.

CONCLUSION

This paper introduced our new 43.5-Gbps bit error rate tester. We aim to enrich our series of bit error testers to continually meet market needs by addressing faster bit rates, developing optical interfaces, and so on.

REFERENCE

1. Suzuki, et.al., "Development of Instruments to Measure 43.5- Gbps Bit Errors," Proceedings of the 2002 Grand Committee of the Institute of Electronics, Information and Communica- tion Engineers (IEICE), Japan, B-10-73