Low Output Capacitance Solid State Relay

KOMACHI Tomonori¹ NAKAYA Makoto¹ TSUHAKO Jyukichi¹

We have developed a solid relay (SSR) with low output capacitance for use in analog LSI test systems. A lateral type DMOS FET was fabricated on a silicon substrate with very low concentration to realize low output capacitance. Drift channel length and drain radius in the drift channel region were optimized to minimize junction capacitance. The drain wire bonding pad was located on the drain junction area to minimize parasitic capacitance.

The SSR was assembled from a DMOS FET with drift channel length Lg=15 μm and drain radius Rd=30 μm, a photovoltanic diode array, and LED in a 6 pin SOP package.

A low-output-capacitance SSR with a breakdown voltage of 200V, on- resistance of 180Ω, and an output capacitance of 2pF was realized.

1. Device Design Center

INTRODUCTION

Yokogawa is the first company to release a hybrid recorder with Solid State Relays (SSR) in 1989. High-reliability has been proven in many fields through over 800,000 channels in comparison with a conventional reed relay using a movable connection.

Many relays are used in an LSI test system as well as in a recorder. A reduction and high-reliability of the semi-conductor evaluation system has been required through remarkable advances in LSI technology and productivity. A Solid State Relay with low output capacitance, which would take place of a reed relay, has been developed for domestic analog LSI test systems.

ABSTRACT OF LOW OUTPUT CAPACITANCE SSR

Figure 1 Low output capacitance DMOSFET chip

A photograph of double diffused MOSFETs (DMOSFET) which is a key device of the low output capacitance SSR is shown in Figure 1. The chip was fabricated by making use of a Yokogawa own developed lateral DMOS process with high breakdown voltage and low leakage current. An example circuit using relays in a LSI test system is indicated in Figure 2. A lot of relays are assembled in a huge matrix to switch signal lines. For a measuring IC's leakage current, all floating capacitance in a measuring system such as relay matrix have to be charged. Therefor a SSR with lower output capacitance has been required in order to reduce setting time. Our aim of the development was to obtain a SSR with low output capacitance of less than 5pF at no bias per one channel and breakdown voltage of over 200V according to the analog IC testing value.

In a typical analog test system signal lines have three different lines. They are force line, sense line and guard line. This time the SSR for switching the sense line or the guard line has been developed because it is available despite its high on-resistance. The SSR switching the force line requires very low on-resistance of less than 1Ω. It is difficult to realize the SSR with high breakdown voltage, low on-resistance and low output capacitance all together in silicon device technology at present. A basic schematic diagram of the SSR is indicated in Figure 3. The light emitted by a LED as an input signal is converted into voltage by a photo voltaic diode allay. The voltage controls the gate terminal of DMOSFETs with low output capacitance. A pair of DMOSFETs is connected in series to pass both positive and negative signals. A shunt resister is inserted between a source and a gate of the DMOSFET to provide a discharge path of the gate charge. That allows DMOSFET to change from on-state to off- state.

Figure 2 An application circuit in analog LSI test system with the low output capacitance SSRs	Figure 3 Schematic diagram of the SSR

DEVICE DESIGN FOR LOW OUTPUT CAPACITANCE

Some technical points of the DMOSFET which is a key device of low output capacitance are discussed in this section. Taking twin DMOSFETs connected in series and a photo voltaic diode array connecting between the source and the gate into account, output capacitance Cout of the SSR is expressed in terms of an equation given by

To design a low output capacitance SSR, drain-source capacitance Cds and drain-gate capacitance Cdg have to be considered.

Figure 4 Cross-section of the lateral DMOSFET

In general power MOSFETs are divided into two types. One is a vertical DMOS with vertical current pass and the other is a lateral DMOS with lateral current pass. A cross section of the lateral DMOS is shown in Figure 4. An oxide film inserted between a drift-channel layer and a overlapped gate metal of the lateral DMOS is thick enough to reduce the drain-gate capacitance Cdg by comparison with the vertical DMOS. If a light doped wafer is utilized, the capacitance between the drift- channel layer and the substrate, drain-source capacitance Cds, is diminished without developing in an advanced fine process. In case of the high breakdown voltage DMOSFET, the lateral DMOS structure allows easy design of low output capacitance compared with the vertical DMOS. Using a lateral DMOS process, the SSR was fabricated.

1. Disign for Drift-Channel Region

Computer simulation was carried out to develop the device. Concentration profiles of the drift-channel region, which determines features of DMOSFET, were calculated by a process simulator. Those results were used for simulation models in a device simulator.

Figure 5 Patterns of DMOSFETs

Breakdown voltage, on-resistance and capacitance are calculated in making use of various parameters such as surface concentration of the drift-channel and the drift-channel length. One of the important parameters in determining breakdown voltage of the lateral DMOS is a drift-channel length Ld between the drain area and the source area as illustrated in Figure 5.

In general the feature of the lateral DMOS, as indicated in Figure 5(a), is that the drain region is surrounded by a gate and a source region like a race track with corners.

Accordingly breakdown voltage is affected by a concentration of electric field which is determined by drain radius Rd at the corner. If drain radius is too small, breakdown voltage of the DMOSFET drops down because of the electric field concentration near the drain. The relation between the drain radius and breakdown voltage is calculated by the device simulator, which solves Poisson's equation in axial coordinate.

2. Feature of the Low Output Capacitance DMOSFET

Output Capacitance of the DMOSFET is determined by drain-source capacitance Cds and drain-gate capacitance Cdg. The drain-source capacitance is determined by the size of junction area between N-type layers and a substrate P- layer which is the same electric potential as the source. The N-type layers over the P- layer are the drain layer and the drift-channel N- layer. In order to decrease the drain-source capacitance, the drain area in the center of the DMOSFET must be minimized. A pad area for wire-bonding of about 100 μm in diameter has to be kept. Extra place except indispensable one was cut down and the feature of the DMOSFET is shown in Figure 5(b). The corner opposite to the drain pad was designed in use an optimum drain radius Rd calculated by the simulator. Curve lines connecting corners to straight lines are smoothly streamlines to avoid a decline of breakdown voltage.

The other point of reducing the output capacitance is to diminish the drain-gate capacitance Cdg. An inversion layer of the silicon surface caused by utilizing a light doped wafer brings about an increase of the drain-gate capacitance Cdg. A gate length was minimized to remove the inversion layer. Keeping the breakdown voltage of DMOSFET, the junction area and the gate length are minimized and the design value was decided by the simulation result.

Figure 6 Cross-section of the drain wire-bonding region

3. Design for Wire-Bonding Pad

A wire-bonding pad of the drain is placed over the junction in this DMOSFET.

Although electric field of the silicon surface is in disorder and the breakdown voltage decreases caused by a wiring of a drain electrode, the wire- bonding pad is able to be set on a field oxide out of drain area in the lateral DMOSFET with 200V breakdown voltage. But parasitic capacitance of the wire-bonding pad brings an increase of the output capacitance of the DMOSFET. Therefore the wire- bonding pad of the drain was set on the drain region. When assembling the SSR, wires are pressed on the wire-bonding pad by ultrasound. So a junction under the wire-bonding pad is directly damaged by the ultrasonic force and that brings bad influence on device characteristics such as an increase of leakage current. Therefore, as shown in Figure 6, the contact of an extracting N+ layer with an electrode metal is designed to be out of the bonding pad area, and an oxide film is inserted below the pad to prevent the junction from damage.

A picture of the SSR with the DMOSFETs which have some technical advances for low output capacitance was shown in Figure 7. A SO package was used for diminishing the output capacitance.

RESULT

Figure 7 Picture of the SSR

The simulation results were compared with the experimental results in detail. A relation between the drift-channel length and the breakdown voltage is indicated in Figure 8. The drift-channel length of 10 to 15 μm is enough to attain the breakdown voltage over 200V.

A relation between the drain radius Rd and the breakdown voltage at 20 μm drift-channel length is shown in Figure 9. If the drain radius Rd is less than 30 μm, the breakdown voltage tend to decline in simulated results which agree with those obtained by experiment.

By making use of the calculated and experimental date, the low output capacitance SSR with the drift-channel length Ld of 15 μm and the drain radius Rd of 30 μm was fabricated. The characteristics of the SSR is shown in Table 1. An obtained value of output capacitance is 1.7 pF compared with object one of 5 pF. Even the sum of the output capacitance and input-to-output capacitance which depends on the package design is reduced below 5 pF. The breakdown voltage is actually around 300V compared with the required value of over 200 V. The value of leakage current is only 10 pA.

Figure 8 Relation between the drift channel length and the breakdown voltage	Figure 9 Relation between the drift radius and the breakdown voltage in case of Ld=20um

Table 1 Characteristics of the low output capacitance SSR (Ta=25°C)

Item	Symbol	Unit	min.	typ.	max	Note.
Load voltage	VBD	V	200
Surge load voltage	Vsurge	V p-p	200			Pw = 800ns T r, T f < Ins
Off-static leakage current	I 1	n A		0.05	1	VD = 100V
On-resistance	R on	Ω		180	220	IF = 5mA VD = 0.2V
Turn on time	τ on	m s		0.01	0.5
Turn off time	τ off	m s		0.1	0.5
Output capacitance	C out	p F		2	5	f = 1 MHz 10 mVrms
Input-to-output Capacitance	C iso	p F		1	2	f = 1MHz 10 mVrms
Isolation voltage	V iso	V rms	2000			AC 1min

CONCLUSION

In summary, the SSR with the low output capacitance has been developed for switching sense or guard line in analog LSI test system. The SSR with the breakdown voltage of 200 V, the on-resistance of 180Ω and the output capacitance of 2 pF was realized. The lateral DMOSFETs were used as switching devices by the use of a light doped wafer for minimizing the low output capacitance. To reduce the junction capacitance, the optimized parameters calculated by a simulator were used for a design of drift-channel region. Compared with a conventional reed relay in a analog LSI test system, the SSR reduced the assembled area by 70% and the volume by 95%.

REFERENCE

M.Nakaya M.Shiraishi M.Ogishima and K.Ishida, "Solid State Relay," Yokogawa Technical Report, No.12, pp. 37 to 40 (1991)