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Virtual Test Verification Environment

PreTestStation™
Allows Early-stage Test Program Verification

The virtual tester PreTestStation™ allows a test program to be verified at an early stage, before a device is completed, without using an actual tester. PreTestStation™ supports the PTS-Virtualizer and PTS-Plus modes. The former uses the same tester OS and debug screen as the actual tester, and is used to mainly verify main programs. The latter mainly verifies the timing of test patterns on the HDL logical simulator by adding responses from a device model. The PTS-plus mode enables test engineers and IC designers to share the same test environment, facilitating highly efficient collaboration in investigating problems. PreTestStation™ reduces LSI test debugging time and testing costs.

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